TY - JOUR
T1 - A pipeline chip for quasi arithmetic coding
AU - Wiseman, Yair
N1 - Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2001/4
Y1 - 2001/4
N2 - A combination of a software and a systolic hardware implementation for the Quasi Arithmetic compression algorithm is presented. The hardware is implemented as a pipeline hardware implementation. The implementation doesn't change the the algorithm. It just split it into two parts. The combination of parallel software and pipeline hardware can give very fast compression without decline of the compression efficiency.
AB - A combination of a software and a systolic hardware implementation for the Quasi Arithmetic compression algorithm is presented. The hardware is implemented as a pipeline hardware implementation. The implementation doesn't change the the algorithm. It just split it into two parts. The combination of parallel software and pipeline hardware can give very fast compression without decline of the compression efficiency.
KW - Compression arithmetic coding
KW - Hardware-software combination
KW - Pipeline structure
UR - http://www.scopus.com/inward/record.url?scp=0035311157&partnerID=8YFLogxK
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AN - SCOPUS:0035311157
SN - 0916-8508
VL - E84-A
SP - 1034
EP - 1041
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IS - 4
ER -