High-Speed Architecture for Hybrid Arithmetic–Huffman Data Compression

This paper proposes a hardware–software co-design for adaptive lossless compression based on Hybrid Arithmetic–Huffman Coding, a table-driven approximation of arithmetic coding that preserves near-optimal compression efficiency while eliminating the multiplicative precision and sequential bottlenecks that have traditionally prevented arithmetic coding deployment in resource-constrained embedded systems. The compression pipeline is partitioned as follows: flexible software on the processor core dynamically builds and adapts the prefix coding (usually Huffman Coding) frontend for accurate probability estimation and binarization; the resulting binary stream is fed to a deeply pipelined systolic hardware accelerator that performs binary arithmetic coding using pre-calibrated finite state transition tables, dedicated renormalization logic, and carry propagation mitigation circuitry instantiated in on-chip memory. The resulting implementation achieves compression ratios consistently within 0.4% of the theoretical entropy limit, multi-gigabit per second throughput in 28 nm/FinFET nodes, and approximately 68% lower energy per compressed byte than optimized software arithmetic coding, making it ideally suited for real-time embedded vision, IoT sensor networks, and edge multimedia applications.