Code generation of graph-based vision processing for multiple CUDA Cores SoC Jetson TX

Elyassaf Madar; Natan Danan; Elishai Ezra Tsur

doi:10.1109/MCSoC2018.2018.00013

Code generation of graph-based vision processing for multiple CUDA Cores SoC Jetson TX

Elyassaf Madar, Natan Danan, Elishai Ezra Tsur

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Embedded vision processing is currently ingrained into many aspects of modern life, from computer-aided surgeries to navigation of unmanned aerial vehicles. Vision processing can be described using coarse-grained data flow graphs, which were standardized by OpenVX to enable both system and kernel level optimization via separation of concerns. Notably, graph-based specification provides a gateway to a code generation engine, which can produce an optimized, hardware-specific code for deployment. Here we provide an algorithm and JAVA-MVC-based implementation of automated code generation engine for OpenVX-based vision applications, tailored to NVIDIA multiple CUDA Cores SoC Jetson TX. Our algorithm pre-processes the graph, translates it into an ordered layer-oriented data model, and produces C code, which is optimized for the Jetson TX1 and comprised of error checking and iterative execution for real time vision processing.

Original language	English
Title of host publication	Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-7
Number of pages	7
ISBN (Electronic)	9781538666890
DOIs	https://doi.org/10.1109/MCSoC2018.2018.00013
State	Published - 16 Nov 2018
Externally published	Yes
Event	12th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018 - Hanoi, Viet Nam Duration: 12 Sep 2018 → 14 Sep 2018

Publication series

Name	Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018

Conference

Conference	12th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018
Country/Territory	Viet Nam
City	Hanoi
Period	12/09/18 → 14/09/18

Bibliographical note

Funding Information:
ACKNOWLEDGMENT The authors would like to thank Tamara Pearlman for her insightful comments. This work was supported by JCT research grant.

Publisher Copyright:
© 2018 IEEE.

Keywords

Embedded computer vision
OpenVX
Visual programming

Access to Document

10.1109/MCSoC2018.2018.00013

Cite this

Madar, E., Danan, N., & Ezra Tsur, E. (2018). Code generation of graph-based vision processing for multiple CUDA Cores SoC Jetson TX. In Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018 (pp. 1-7). Article 8540206 (Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MCSoC2018.2018.00013

Madar, Elyassaf ; Danan, Natan ; Ezra Tsur, Elishai. / Code generation of graph-based vision processing for multiple CUDA Cores SoC Jetson TX. Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1-7 (Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018).

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abstract = "Embedded vision processing is currently ingrained into many aspects of modern life, from computer-aided surgeries to navigation of unmanned aerial vehicles. Vision processing can be described using coarse-grained data flow graphs, which were standardized by OpenVX to enable both system and kernel level optimization via separation of concerns. Notably, graph-based specification provides a gateway to a code generation engine, which can produce an optimized, hardware-specific code for deployment. Here we provide an algorithm and JAVA-MVC-based implementation of automated code generation engine for OpenVX-based vision applications, tailored to NVIDIA multiple CUDA Cores SoC Jetson TX. Our algorithm pre-processes the graph, translates it into an ordered layer-oriented data model, and produces C code, which is optimized for the Jetson TX1 and comprised of error checking and iterative execution for real time vision processing.",

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year = "2018",

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Madar, E, Danan, N & Ezra Tsur, E 2018, Code generation of graph-based vision processing for multiple CUDA Cores SoC Jetson TX. in Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018., 8540206, Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018, Institute of Electrical and Electronics Engineers Inc., pp. 1-7, 12th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018, Hanoi, Viet Nam, 12/09/18. https://doi.org/10.1109/MCSoC2018.2018.00013

Code generation of graph-based vision processing for multiple CUDA Cores SoC Jetson TX. / Madar, Elyassaf; Danan, Natan; Ezra Tsur, Elishai.
Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-7 8540206 (Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Madar E, Danan N, Ezra Tsur E. Code generation of graph-based vision processing for multiple CUDA Cores SoC Jetson TX. In Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-7. 8540206. (Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018). doi: 10.1109/MCSoC2018.2018.00013

Code generation of graph-based vision processing for multiple CUDA Cores SoC Jetson TX

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

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