A pipeline chip for quasi arithmetic coding

Yair Wiseman

Research output: Contribution to journalArticlepeer-review


A combination of a software and a systolic hardware implementation for the Quasi Arithmetic compression algorithm is presented. The hardware is implemented as a pipeline hardware implementation. The implementation doesn't change the the algorithm. It just split it into two parts. The combination of parallel software and pipeline hardware can give very fast compression without decline of the compression efficiency.

Original languageEnglish
Pages (from-to)1034-1041
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number4
StatePublished - Apr 2001
Externally publishedYes


  • Compression arithmetic coding
  • Hardware-software combination
  • Pipeline structure


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